1. Field of the Invention
The present invention relates to a semiconductor device structure having an interlayer dielectric film made of a resinous material. The invention also relates to a method of fabricating such a semiconductor device structure.
2. Description of the Related Art
Techniques for fabricating thin-film transistors (TFTs), using a thin film semiconductor formed on a glass substrate or quartz substrate, have been known.
The prior art steps for fabricating a TFT are shown in FIGS. 3(A) and 3(B). This TFT is disposed in a pixel region of an active matrix liquid crystal display.
First, a silicon oxide film is formed as a buffer layer 302 on a substrate 301 of glass or quartz to a thickness of 3000 xc3x85 by plasma CVD. Then, an amorphous silicon film (not shown) is formed to a thickness of about 500 to 1500 xc3x85 by plasma CVD or LPCVD. This amorphous film acts as a starting film in forming an active layer of TFTs. Subsequently, the amorphous silicon film (not shown) is heat-treated or illuminated with laser light to crystallize the amorphous film. In this way, a crystalline silicon film (not shown) is obtained.
Then, this crystalline silicon film is patterned to form regions (303, 304, 305 in FIG. 3(A)) which will become the active layer of the TFTs later. Thereafter, a silicon oxide film 306 which covers the active layer and acts as a gate-insulating film is formed to a thickness of 1000 to 1500 xc3x85 by plasma CVD. Then, a gate electrode 307 is formed from a metallic material or silicide material. Thus, a state shown in FIG. 3(A) is obtained. Under this condition, dopant ions are implanted, and the source region 303, the drain region 305, and the channel formation region 304 are formed by self-aligned technology. This is followed by heat-treatment or laser illumination, for annealing the doped regions.
Then, a first dielectric film 308 is formed from silicon nitride or silicon oxide to a thickness of 2000 to 6000 xc3x85 by plasma CVD. Subsequently, contact holes are formed. A source electrode and interconnects, 309, extending from it are formed from an appropriate metal material (FIG. 3(B)).
Then, a second interlayer dielectric film 310 is formed from silicon oxide or silicon nitride. The thickness of this second interlayer dielectric film is set greater than 7000 xc3x85 to assure that the surface is sufficiently flat. Then, a contact hole 311 is formed, thus obtaining a state shown in FIG. 3(C).
Thereafter, an ITO electrode 312 forming a pixel electrode is formed. In consequence, a TFT disposed in the pixel region of the active matrix regions is completed. During these fabrication steps, the formation of the pixel electrode 312 presents the following problems.
In recent years, the sizes of conductor patterns and TFT patterns have tended to diminish, because there is an increasing demand for increased device densities. Furthermore, active matrix liquid crystal displays are required to reduce such patterns to increase the aperture ratio of pixels.
As such patterns are reduced in size, it is, of course, necessary to reduce the size of the window hole 311. However, if the contact hole 311 is reduced in size, the material, or ITO, of the pixel electrode 312 does not form a film with good coverage within the small hole. As a result, it is difficult to make required contacts. In particular, the contact hole is elongated. The material for making a contact may break inside the hole. As a consequence, poor contact takes place.
It is an object of the present invention to provide techniques for solving problems associated with poor contact caused as finer-line patterns are utilized.
An embodiment of the present invention described herein is shown in FIGS. 1(A)-1(C), where a semiconductor device has a multilayer dielectric film consisting of dielectric layers 114, 116, and 117. The top layer 117 is made of a resinous material. A contact hole 119 is formed in the multilayer dielectric film. This structure is characterized in that the resinous material portion around the contact hole 119 is overetched, as indicated by 100 in FIG. 2(A).
The use of this structure permits finer-line geometries. Even if the contact area decreases, it is assured that contact to a source region 110 is made by an electrode 120 consisting of a metallization level. Furthermore, this metallization level 120 is prevented from breaking, by tapering the overetched portion 100.
Moreover, the planarity of the surface is assured by forming the top layer 117 from a resinous material. Therefore, the electric field applied from the pixel electrode is not disturbed.
Another embodiment of the invention is a method of fabricating a semiconductor device. This method is illustrated in FIGS. 1(A)-1(C). This method is initiated with forming a dielectric film 116 from a silicide. Then, a dielectric film 117 is formed from a resinous material on the silicide film (a silicon-containing dielectric film). As a result, a lamination film consisting of the silicide layer 116 and the resinous layer 117 is obtained. A contact hole 119 is formed in the lamination film. The resinous layer 117 is isotropically etched, using a means capable of selectively etching the resinous material, to overetch the opening in the contact hole 119, thus forming a window hole 201.
By etching only the resinous material selectively, the window hole 119 is widened and assumes a form which facilitates making a contact. Furthermore, the tapering portion 100 can be formed by the use of isotropic etching. Hence, electrodes and conductors formed over the tapering portion 100 do not break. The aforementioned silicide (silicon-containing dielectric) can be silicon oxide, silicon nitride, or silicon oxynitride.